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LAN9211 Datasheet(PDF) 89 Page - SMSC Corporation

Part # LAN9211
Description  High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
PDF  146 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN9211 Datasheet(HTML) 89 Page - SMSC Corporation

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC
LAN9211
89
Revision 1.93 (11-27-07)
DATASHEET
16-19
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX Status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See Section 5.3.9.1, "Allowable settings for
Configurable FIFO Memory Allocation," on page 91 for more information.
R/W
5h
15-14
Reserved
RO
-
13-12
Threshold Control Bits (TR). These control the transmit threshold values
the MIL should use. These bits are used when the SF bit is reset. The host
can program the Transmit threshold by setting these bits. The intent is to
allow the MIL to transfer data to the final destination only after the threshold
value is met.
In 10Mbps mode (TTM = 1) the threshold is set as follows:
In 100Mbps mode (TTM = 0) the threshold is set by as follows:
R/W
00
11-2
Reserved
RO
-
1
Soft Reset Timeout (SRST_TO). If a software reset is attempted when the PHY
is not in the operational state (RX_CLK and TX_CLK running), the reset will not
complete and the soft reset operation will timeout and this bit will be set to a ‘1’. The
host processor must correct the problem and issue another soft reset.
RO
0
BITS
DESCRIPTION
TYPE
DEFAULT
[13]
[12]
Threshold (DWORDS)
0
0012h
0
1
018h
1
0
020h
1
1
028h
[13]
[12]
Threshold (DWORDS)
0
0020h
0
1
040h
1
0
080h
1
1
100h



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