RZSLASHG3E datasheet(5/112 Pages) RENESAS

5 / 112 page

RZ/G3E Group

1. Overview

R01DS0477EJ0115 Rev.1.15

Page 5 of 112

Nov 28, 2025

1.1.6

Internal Memory

Item

Description

System RAM

● 512 Kbytes (with ECC)

1.1.7

External Memory Interface

Item

Description

External Bus Controller for

LPDDR4/4X SDRAM

(DDR)

● 1 channel

● Support LPDDR4X-3200

Bus width: 32-bit

Memory Size: Up to 4 GBytes, Single rank (15 mm PKG, 21 mm PKG)

● Support LPDDR4-3200

Bus width: 32-bit

Memory Size: Up to 4 GBytes, Single rank (15 mm PKG, 21 mm PKG)

Memory Size: Up to 8 GBytes, Dual rank (15 mm PKG)

● In line ECC supported (support for error detection interrupts)

● Auto Refresh/Self Refresh/IO Retention supported

● Memory access protection for secure regions using TZC-400 (Arm® TrustZone® supported)

xSPI Controller

(xSPI)

● 1 channel (2 chip select signals)

● Compliant with the xSPI protocol

● Protocol mode

1, 4, or 8 pins with SDR or DDR (1S-1S-1S, 4S-4D-4D*1, 8D-8D-8D*1)

2 or 4 pins with SDR (1S-2S-2S, 2S-2S-2S, 1S-4S-4S, 4S-4S-4S)

● Support for XiP mode

● Support for up to 256-Mbyte address space (support for up to 128 Mbytes per channel address

space in boot sequence)

SD Card Host Interface/

Multimedia Card Interface

(SD/MMC)

● 3 channels

Channel 0 supports SDHI/e-MMC (boot supported)

Channel 1 supports SDHI/e-MMC

Channel 2 supports SDHI

● SD memory I/O card interface (1-bit/4-bit SD bus)

● SD, SDHC and SDXC SD memory card access supported

● Compliant with SD specification version 3.01

● Default, high-speed, UHS-I/SDR50, SDR104 and DDR50 transfer modes supported

● Error check function: CRC7 (Command), CRC16 (Data)

● Support for card detection and write protection

● MMC interface

Channel 0 (1-bit/4-bit/8-bit MMC bus)

Channel 1 (1-bit/4-bit MMC bus)

● e-MMC device access supported

● Compliant with eMMC 4.51

● High-speed, HS200 and HS-DDR transfer modes supported

Note 1.

DDR access without DS (XSPI0_DS) is not supported.

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