RZSLASHG3E datasheet(95/112 Pages) RENESAS

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RZ/G3E Group

3. Electrical Characteristics

R01DS0477EJ0115 Rev.1.15

Page 95 of 112

Nov 28, 2025

3.5.21

PDM Timing

Conditions:

VOH = VDD18 × 0.5, VOL = VDD18 × 0.5, C = 30 pF (1.8 V)

VOH = VDD33 × 0.5, VOL = VDD33 × 0.5, C = 30 pF (3.3 V)

Drive strength: ×1, ×2, ×4, ×6

Table 3.30

PDM Interface Timing

Parameter

Symbol

Min.

Max.

Unit

Figure

Clock period

tPSYNC

tCCcyc = 208.33 ns

(4.8 MHz)*1

Figure 3.64

Clock high-level period

tPDCKWH

tPSYNC × 0.45

tPSYNC × 0.55

Clock low-level period

tPDCKWL

tPSYNC × 0.45

tPSYNC × 0.55

Clock rise time

tR-EDGE

—

3*2

Clock fall time

tF-EDGE

—

3*2

Setup time

tsu

—

Figure 3.65,

Figure 3.66

Hold time

—

Note 1.

tCCcyc is the period of PDM_n_CCLK (n = 0, 1).

Note 2.

Output transition time from 20% to 80%

PDMCLKnm

tPDCKWH

tPDCKWL

tPSYNC

tR-EDGE

tF-EDGE

n = 0, 1

m = 0 to 2

Figure 3.64

Timing of Clock Output (PDMCLKnm)

PDMCLKnm

(Output)

tSU

PDMDATnm

(Input)

n = 0, 1

m = 0 to 2

Figure 3.65

Timing of Clock Output (Synchronized with the rise of PDMCLKnm)

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