RZSLASHG3E datasheet(92/112 Pages) RENESAS

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RZ/G3E Group

3. Electrical Characteristics

R01DS0477EJ0115 Rev.1.15

Page 92 of 112

Nov 28, 2025

3.5.20

SSIU Timing

Condition:

VOH = VDD18 × 0.5, VOL = VDD18 × 0.5, C = 30 pF*1 (1.8 V)

VOH = VDD33 × 0.5, VOL = VDD33 × 0.5, C = 30 pF*1 (3.3 V)

Drive strength: ×1, ×2, ×4, ×6

Note 1.

Other than tRC: Rise-edge clock timing

Table 3.29

SSIU Signal Timing

Parameter

Symbol

Min.

Max.

Unit

Note

Figure

Output clock cycle

15625

—

Figure 3.59

Input clock cycle

15625

—

Output clock high-cycle

tHC

35*1

—

Output clock low-cycle

tLC

35*1

—

Input clock high-cycle

tHC

—

Input clock low-cycle

tLC

—

Rise-edge clock timing

tRC

—

20*2

Output (100 pF)

Output delay

-5

—

Figure 3.60 to

Figure 3.63

Setup time

—

Hold time

—

Note 1.

The width at high or low level of the clock signal when the input on AUDIO_CLKA, AUDIO_CLKB, or AUDIO_CLKC is output

from SCK without frequency division in master mode is min. 30 ns.

The relevant registers are as follows:

ADG: Audio Clock Select Register m (AUDIO_CLK_SELm (m = 0 to 2))

SSIU: Control Register (SSICRn (n = 0 to 9))

Note 2.

Output transition time from 20% to 80%

tHC

tLC

tRC

tI, tO

SSIn_SCK

Figure 3.59

SCK Clock Input/Output Timing

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