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RZ/G3E Datasheet(PDF) 80 Page - Renesas Technology Corp

Part # RZ/G3E
Description  RZ Family, RZ/G Series
PDF  112 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RZ/G3E Datasheet(HTML) 80 Page - Renesas Technology Corp

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RZ/G3E Group
3. Electrical Characteristics
R01DS0477EJ0115 Rev.1.15
Page 80 of 112
Nov 28, 2025
Table 3.24
IIC Timing (HS mode)
Cb = 100 pF
Cb = 400 pF
Parameter
Symbol
Min.*1
Max.
Min.*1
Max.
Unit
Figure
IIC (HS
mode)
SCL3n cycle time
tSCL
3(36) × tIICcyc + 4 × tPcyc +
240
—
3(36) × tIICcyc + 4 × tPcyc +
240
—
ns
Figure
3.47
SCL3n high-level pulse
width
tSCLH
2(18) × tIICcyc + 2 × tPcyc +
120
—
2(18) × tIICcyc + 2 × tPcyc +
120
—
ns
SCL3n low-level pulse
width
tSCLL
2(18) × tIICcyc + 2 × tPcyc +
120
—
2(18) × tIICcyc + 2 × tPcyc +
120
—
ns
SCL3n rise time
tSr
—
40
—
80
ns
SCL3n rise time after a
repeated START
condition and after an
acknowledge bit
tSr
—
80
—
160
ns
SDA3n rise time
tSr
—
80
—
160
ns
SCL3n fall time
tSf
—
40
—
80
ns
SDA3n fall time
tSf
—
80
—
160
ns
SCL3n, SDA3n spike
pulse removal time
tSP
0
1(16) ×
tIICcyc
0
1(16) ×
tIICcyc
ns
Hold time for START
condition
tSTAH
tIICcyc + 135
—
tIICcyc + 135
—
ns
Setup time for repeated
START condition
tSTAS
160
—
160
—
ns
Setup time for STOP
condition
tSTOS
160
—
160
—
ns
Data setup time
tSDAS
10
—
10
—
ns
Data hold time
tSDAH
0
80
0
150
ns
SCL3n, SDA3n
capacitive load
Cb
—
100
—
400
pF
Note 1.
tIICcyc: I3C internal reference clock (I3Cϕ) cycle, tPcyc: I3C_0_TCLK cycle. Values in parentheses apply when INCTL.DNFS[3:0]
is set to 1111b while the digital filter is enabled with INCTL.DNFE set to 1b
Note 2.
The maximum SCL clock frequency is 1.7 MHz.



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