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RZ/G3E Datasheet(PDF) 78 Page - Renesas Technology Corp |
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RZ/G3E Datasheet(HTML) 78 Page - Renesas Technology Corp |
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78 / 112 page  RZ/G3E Group 3. Electrical Characteristics R01DS0477EJ0115 Rev.1.15 Page 78 of 112 Nov 28, 2025 3.5.17 I3C Timing Conditions: VOH = VDD1218_I3C × 0.5, VOL = VDD1218_I3C × 0.5, C = 30 pF (1.2 V or 1.8 V) Drive strength: ×6 Table 3.22 I3C Timing Parameter Symbol Min.*1 Max. Unit Figure IIC (Standard mode, SMBus) SCL3n cycle time tSCL 4(36) × tIICcyc + 4 × tPcyc + 1300 — ns Figure 3.47 SCL3n high-level pulse width tSCLH 2(18) × tIICcyc + 2 × tPcyc + 300 — ns SCL3n low-level pulse width tSCLL 2(18) × tIICcyc + 2 × tPcyc + 800 — ns SCL3n, SDA3n rise time tSr — 1000 ns SCL3n, SDA3n fall time tSf — 300 ns SCL3n, SDA3n spike pulse removal time tSP 0 1(16) × tIICcyc ns SDA3n bus free time tBUF 3(20) × tIICcyc + 300 — ns Hold time for START condition tSTAH tIICcyc + 300 — ns Setup time for repeated START condition tSTAS 1000 — ns Setup time for STOP condition tSTOS 1000 — ns Data setup time tSDAS tIICcyc + 50 — ns Data hold time tSDAH 0 — ns SCL3n, SDA3n capacitive load Cb — 400 pF IIC (Fast mode) SCL3n cycle time tSCL 4(36) × tIICcyc + 4 × tPcyc + 600 — ns Figure 3.47 SCL3n high-level pulse width tSCLH 2(18) × tIICcyc + 2 × tPcyc + 300 — ns SCL3n low-level pulse width tSCLL 2(18) × tIICcyc + 2 × tPcyc + 300 — ns SCL3n, SDA3n rise time tSr — 300 ns SCL3n, SDA3n fall time tSf — 300 ns SCL3n, SDA3n spike pulse removal time tSP 0 1(16) × tIICcyc ns SDA3n bus free time tBUF 3(20) × tIICcyc + 300 — ns Hold time for START condition tSTAH tIICcyc + 300 — ns Setup time for repeated START condition tSTAS 300 — ns Setup time for STOP condition tSTOS 300 — ns Data setup time tSDAS tIICcyc + 50 — ns Data hold time tSDAH 0 — ns SCL3n, SDA3n capacitive load Cb — 400 pF Note 1. tIICcyc: I3C internal reference clock (I3Cϕ) cycle, tPcyc: I3C_0_TCLK cycle. Values in parentheses apply when INCTL.DNFS[3:0] is set to 1111b while the digital filter is enabled with DNFE.DNFE set to 1b. |
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