RZSLASHG3E datasheet(10/112 Pages) RENESAS

10 / 112 page

RZ/G3E Group

1. Overview

R01DS0477EJ0115 Rev.1.15

Page 10 of 112

Nov 28, 2025

1.1.12

Peripheral Module

Item

Description

I3C Bus Interface

(I3C)

● 1 channel

● Support for 1.2 V and 1.8 V

● Master or Slave mode selectable

● Support for the multi-master

● Compliant with MIPI I3C v1.0 and I3C Basic v1.0

● The following functions are not supported:

– Bridge device (I3C v1.0 and I3C Basic v1.0)

– Asynchronous timing control async mode 2 & 3 (I3C v1.0)

● Support for DMAC and event linking

I2C Bus Interface

(RIIC)

● 9 channels

● Master or Slave mode selectable

● Support for the multi-master

● Support for Standard mode (100 kHz), Fast mode (400 kHz), and Fast mode+ (1 MHz)

● Support for DMAC and event linking

Renesas Serial

Communication Interface

(RSCI)

● 10 channels

● 6 communication mode

– Asynchronous interfaces

– 8-bit clock synchronous interface

– Simple IIC (master-only)

– Simple SPI

– Smart card interface

– Simple LIN (expanded SCIX mode)

● 32-stage FIFO registers for transmission and reception

● Clock sources is select from among four internal clock signals

● Bit rate specifiable with the on-chip baud rate generator

● Full-duplex and Half-duplex communication

● Data length: 7 to 9 bits

● Bit rate modulation

● Double speed mode

● Loopback function to enable self-diagnosis

● Support for DMAC and event linking

● Support for CRC calculation by the CRC unit

Renesas Serial Peripheral

Interface

(RSPI)

● 3 channels

● SPI transfer facility

– Using the MOSI (master out slave in), MISO (master in slave out), SSL (slave select), and

RSPCK (SPI clock) signals enables serial transfer through SPI operation (four lines) or clock-

synchronous operation (three lines)

– Capable of handling serial transfer as a master or slave

● Data formats

– Switching between MSB first and LSB first

– The number of bits in each transfer can be changed to any number of bits from 8 to 16, or 20,

24, or 32 bits.

– 32 bits × 16 stage buffers for transmission and reception

– Up to for frames can be transmitted or received in a single transfer operation (with each frame

having up to 32 bits)

● Buffered structure

– 16 stages/channels for MOSI and MISO independently

– Double buffers for both transmission and reception

● RSPCK can be stopped automatically with the reception buffer full for master reception

● Support for DMAC and event linking

● Support CRC calculation by the CRC unit

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