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RZ/G3E Datasheet(PDF) 76 Page - Renesas Technology Corp |
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RZ/G3E Datasheet(HTML) 76 Page - Renesas Technology Corp |
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76 / 112 page  RZ/G3E Group 3. Electrical Characteristics R01DS0477EJ0115 Rev.1.15 Page 76 of 112 Nov 28, 2025 3.5.16 Renesas IIC Bus Interface (RIIC) Access Timing Conditions: VOL = 0.4 V Drive strength: ×6 Table 3.21 RIIC Timing Parameter Symbol Min.*1,*2 Max.*1,*2 Unit Figure RIIC (Standard- mode) SCL input cycle time tSCL 6(12) × tIICcyc + 1300 — ns Figure 3.46 SCL input high-level pulse width tSCLH 3(6) × tIICcyc + 300 — ns SCL input low-level pulse width tSCLL 3(6) × tIICcyc + 300 — ns SCL, SDA input rise time tsr — 1000 ns SCL, SDA input fall time tsf — 300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 1000 — ns Stop condition input setup time tSTOS 1000 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load Cb — 400 pF RIIC (Fast- mode) SCL input cycle time tSCL 6(12) × tIICcyc + 600 — ns Figure 3.46 SCL input high-level pulse width tSCLH 3(6) × tIICcyc + 300 — ns SCL input low-level pulse width tSCLL 3(6) × tIICcyc + 300 — ns SCL, SDA input rise time tsr —*4 300 ns SCL, SDA input fall time tsf —*4 300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 300 — ns Stop condition input setup time tSTOS 300 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load*3 Cb — 400 pF RIIC (Fast- mode Plus) SCL input cycle time tSCL 6(12) × tIICcyc + 240 — ns Figure 3.46 SCL input high-level pulse width tSCLH 3(6) × tIICcyc + 120 — ns SCL input low-level pulse width tSCLL 3(6) × tIICcyc + 120 — ns SCL, SDA input rise time tsr —*4 120 ns SCL, SDA input fall time tsf —*4 120 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 120 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 300 — ns Stop condition input setup time tSTOS 300 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0 — ns SCL, SDA capacitive load*3 Cb — 550 pF |
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