RZSLASHG3E datasheet(6/112 Pages) RENESAS

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RZ/G3E Group

1. Overview

R01DS0477EJ0115 Rev.1.15

Page 6 of 112

Nov 28, 2025

1.1.8

CPU Peripheral

Item

Description

Clock Pulse Generator

(CPG)

● Generates the clocks from an external clock or external resonator (24 MHz).

– Maximum Arm Cortex-A55 clock: 1.8 GHz with Over Drive (0.9 V)

– Maximum Arm Cortex-M33 clock: 200 MHz

– Maximum DDR clock: 800 MHz (LPDDR4/4X-3200)

– Maximum 3DGE clock: 630 MHz

– Maximum VSP clock: 800 MHz

– Maximum NPU clock: 1.0 GHz

– Maximum H.264/H.265 clock: 400 MHz

– Maximum System Bus clock: 400 MHz

● SSC (Spread Spectrum Clock) supported

Direct Memory Access

Controller

(DMAC)

● 80 channels

● Transfer modes: Single transfer mode and block transfer mode

● LINK mode (DMA transfer under descriptor control) supported

● Transfer size: 1, 2, 4, 8, 16, 32, 64, or 128 bytes

● Transfer request: Software trigger, external DMA requests (DREQ) and interrupt requests from

peripheral functions

● A specific DMA transfer interval can be specified to adjust the bus occupancy.

Interrupt Controller

● Arm® CoreLinkTM Generic Interrupt Controller (GIC-600) for Arm Cortex-A55 (32 priority levels

available)

● Nested Vectored Interrupt Controller (NVIC) for Arm Cortex-M33

● External Interrupt pins (NMI, IRQ0 to IRQ15, and TINT0 to TINT31)

● On-chip peripheral Interrupts: priority level set for each module

Event Link Controller

(ELC)

● Up to 455 event signals can be interlinked with the operation of modules

● In particular, the operation of timer modules can be started by input event signals

● Event-linked operation of signals of 16 ports P10~17, P70~77 is to be possible.

Error Controller

● Error events from CPU and peripherals are captured and merged to interrupt with mask for Arm

Cortex-A55 and Arm Cortex-M33 respectively.

● System reset can be generated by error events.

Message Handling Unit

(MHU)

● Message handling function between Arm Cortex-A55 and Arm Cortex-M33

● Assert interrupt to inform message and response from/to every core

General-purpose I/O

(GPIO)

● 141 General-purpose I/O ports

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