RZSLASHG3E datasheet(63/112 Pages) RENESAS

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RZ/G3E Group

3. Electrical Characteristics

R01DS0477EJ0115 Rev.1.15

Page 63 of 112

Nov 28, 2025

Table 3.18

xSPI Timing (2/2)

1.8 V

3.3 V

Parameter

Symbol

Min.

Max.

Min.

Max.

Unit

Figure

DS low to CS high

tDSLCSH

tPERIOD × 0.8*7 —

Figure 3.29

CS high to DS Tri-state

tCSHDST

0.0

tPERIOD

0.0

tPERIOD

CS low to DS low*5

tCSLDSL

0.0

12.5*6

0.0

17.4*6

DS Tri-state to CS low

tDSTCSL

0.0

—

0.0

—

CK low to DS low*8

tCKLDSL

—

(0.45 + e) ×

tPERIOD – 2.0*9

—

(0.45 + e) ×

tPERIOD – 2.0*9

Note: CK: XSPI0_CKP (XSPI0_CKN)

DS: XSPI0_DS

CS: XSPI0_CS0N, XSPI0_CS1N

Note 1.

Specification at 133 MHz / Specification at 100 MHz

Note 2.

These are values when the OEN assertion is extended in the Output Enable Asserting extension bit (COMCFG.OEASTEX =

1b).

Note 3.

These are the values when the CS assertion is extended in the CS asserting extension bit (LIOCFGCSn.CSASTEX = 1b).

Note 4.

The standard value for xSPI266 is 0.8 ns.

Note 5.

If the DS is high during the command & modifier phase when using JESD251 Profile 2.0 memory, the time from CS low to DS

high must also meet this specification.

Note 6.

When using JESD251 Profile 1.0 memory or JESD251 Profile 2.0 memory with LIOCFGCSn.LATEMD set to 0, this constraint

does not apply if the internal pull-down resistor of the DS pin is enabled.

Note 7.

These are the values when the tCKLDSL constraint is satisfied.

Note 8.

This constraint is necessary only to satisfy the tDSLCSH requirement specified in JESD251, which specifies that tDSLCSH must be

at least 80% of tPERIOD. Set LIOCFGCSn.CSNEGEX to the appropriate value to ensure the memory specification complies with

this constraint.

Note 9.

e: LIOCFGCSn.CSNEGEX (e = 0, 1)

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