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RZ/G3E Datasheet(PDF) 82 Page - Renesas Technology Corp |
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RZ/G3E Datasheet(HTML) 82 Page - Renesas Technology Corp |
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82 / 112 page ![]() RZ/G3E Group 3. Electrical Characteristics R01DS0477EJ0115 Rev.1.15 Page 82 of 112 Nov 28, 2025 Table 3.25 I3C Timing (Open Drain Timing Parameters) Parameter Symbol Min.*1 Max. Unit Figure Notes SCL3n clock Low period tLOW_OD 200 — ns Figure 3.50 1, 2 tDIG_OD_L tLOW_ODmin + tfDA_ODmin — ns Figure 3.50 — SCL3n clock High period tHIGH — 41 ns Figure 3.50 3, 4 tDIG_H 36 (when 1.8 V) 40 (when 1.2 V) tHIGH + tCF ns Figure 3.50 SDA3n signal fall time tfDA_OD tCF 33 ns Figure 3.50 — SDA3n data setup time open drain mode VDD1218 = 1.8 V tSU_OD 12 — ns Figure 3.49, Figure 3.50 1 VDD1218 = 1.2 V 13.9 — ns Clock after START (S) condition tCAS 38.4 For ENTAS0: 1 µ seconds Figure 3.50 5, 6 For ENTAS1: 100 µ For ENTAS2: 2 m For ENTAS3: 50 m Clock before STOP (P) condition tCBP tCASmin/2 — seconds Figure 3.51 — Current master to secondary master overlap time during handoff tMMOverlap tDIG_OD_Lmin — ns Figure 3.56 — Bus available condition tAVAL 1 — µs — 7 Bus idle condition tIDLE 1 — ms — — Time internal where new master not driving SDA3n low tMMLock tAVALmin — µs Figure 3.56 — Note 1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_ODmin. Note 2. The Master may use a shorter Low period if it knows that this is safe, i.e., that SDA is already above VIH. Note 3. This is based on tSPIKE, rise and fall times, and interconnect. Note 4. This maximum High period may be exceeded when the signals can be safely seen by Legacy I2C Devices, and/or in consideration of the interconnect (e.g., a short bus). Note 5. On a Legacy Bus where I2C Devices need to see Start. Note 6. Slaves that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3 Note 7. On a Mixed Bus with Fm Legacy I2C Devices, tAVAL is 300 ns shorter than the Fm Bus Free Condition time (tBUF) |
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