RZSLASHG3E datasheet(83/112 Pages) RENESAS

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RZ/G3E Group

3. Electrical Characteristics

R01DS0477EJ0115 Rev.1.15

Page 83 of 112

Nov 28, 2025

Table 3.26

I3C Timing (Push-Pull Timing Parameters for SDR)

Parameter

Symbol

Min.*1

Max.

Unit

Figure

Notes

SCL3n clock

frequency

VDD1218 = 1.8 V

tSCL

0.01

12.5

MHz

—

VDD1218 = 1.2 V

0.01

12.39

MHz

—

SCL3n clock Low period

tLOW

—

Figure 3.48

—

tDIG_L

—

Figure 3.48

2, 4

SCL3n clock High period for Mixed Bus

tHIGH

—

Figure 3.48

—

tDIG_H

Figure 3.48

2, 3

SCL3n clock High period

tHIGH

—

Figure 3.48

—

tDIG_H

Figure 3.48

Clock in to data out

for a slave

VDD1218 = 1.8 V

tSCO

—

Figure 3.53

—

VDD1218 = 1.2 V

—

12.7

SCL3n clock rise time

tCR

—

150 × 1/fSCL

(capped at 60)

Figure 3.48

—

SCL3n clock fall time

tCF

—

150 × 1/fSCL

(capped at 60)

Figure 3.48

—

SDA3n signal data

hold in push-pull

mode

Master

tHD_PP

tCR + 3 and tCF + 3

—

Figure 3.52

Slave

—

Figure 3.54

—

SDA3n signal data

setup in push-pull

mode

VDD1218 = 1.8 V

tSU_PP

N/A

Figure 3.52,

Figure 3.53,

Figure 3.54

—

VDD1218 = 1.2 V

13.9

N/A

Clock after repeated START (Sr)

tCASr

tCASmin

N/A

Figure 3.55

—

Clock before repeated START (Sr)

tCBSr

tCASmin/2

N/A

Figure 3.55

—

Capacitive load per bus line (SDA3n /

SCL3n)

—

Note 1.

FSCL = 1/(tDIG_L + tDIG_H)

Note 2.

tDIG_L and tDIG_H are the clock Low and High periods as seen at the receiver end of the I3C Bus using VIL and VIH (see

Figure

3.48)

Note 3.

When communicating with an I3C Device on a mixed bus, the tDIG_H_MIXED period must be constrained in order to make sure

that I2C Devices do not interpret I3C signaling as valid I2C signaling.

Note 4.

As both edges are used, the hold time must be satisfied for the respective edges, for example, tCF + 3 for falling edge clocks,

and tCR + 3 for rising edge clocks.

0.7×VDD

0.3×VDD

tHIGH

SCL3n

tCF

tLOW

tCR

tDIG_H

tDIG_L

Note: VDD: VDD1218_I3C

Figure 3.48

tDIG_H and tDIG_L

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