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RZ/G3E Datasheet(PDF) 67 Page - Renesas Technology Corp |
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RZ/G3E Datasheet(HTML) 67 Page - Renesas Technology Corp |
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67 / 112 page ![]() RZ/G3E Group 3. Electrical Characteristics R01DS0477EJ0115 Rev.1.15 Page 67 of 112 Nov 28, 2025 Table 3.19 RSCI Timing (2/2) Parameter Symbol Min. Max. Unit Figure RSCI (Clock sync, Simple SPI) SCK output clock cycle (master) tSPcyc 4 65536 tPSCIcyc Figure 3.32 to Figure 3.37 SCK input clock cycle (slave) 4 65536 tPSCIcyc SCK clock high-level pulse width tSPCKWH 0.4 0.6 tSPcyc SCK clock low-level pulse width tSPCKWL 0.4 0.6 tSPcyc Input clock rise time tSPCKR — 3 ns Input clock fall time tSPCKF — 3 ns Output clock rise time VDD1833 = 1.8 V tSPCKR — 6.18*2 ns VDD1833 = 3.3 V — 7.9*2 ns Output clock fall time VDD1833 = 1.8 V tSPCKF — 6.18*2 ns VDD1833 = 3.3 V — 7.9*2 ns Data input setup time Internal clock tSU 7 — ns External clock 3 — ns Data input hold time Internal clock tH 3 — ns External clock 3 — ns Data output delay time Internal clock tOD — 3 ns External clock — 12 ns Data output hold time Internal clock tOH −3 — ns External clock 0 — ns Data rise/fall time VDD1833 = 1.8 V tDR, tDF — 6.18*2 ns VDD1833 = 3.3 V — 7.9*2 ns Slave access time Internal clock tSA — 3 × tPSCIcyc + 12 ns External clock — 3 × tPSCIcyc + 12 ns Slave output release time Internal clock tREL — 3 × tPSCIcyc + 12 ns External clock — 3 × tPSCIcyc + 12 ns RSCI (Simple SPI) SS input setup time tLEAD 1 — tSPcyc Figure 3.32 to Figure 3.37 SS input hold time tLAG 1 — tSPcyc SS input rise/fall time tSSR, tSSF — 3 ns Note: tPSCIcyc: RSCI_n_TCLK cycle (n = 1 to 9) Note 1. NFcyc = 4p × 2q − 1 × tPSCIcyc p: CCR2.CKS[1:0] (p = 0, 1, 2, 3) q: CCR1.NFCS[2:0] (q = 1, 2, 3, 4) Note 2. Output transition time from 20% to 80% SCKn (n = 0 to 9) tScyc tSCKW tSCKf tSCKr Figure 3.30 SCK Clock Input/Output Timing |
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