RZSLASHG3E datasheet(71/112 Pages) RENESAS

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RZ/G3E Group

3. Electrical Characteristics

R01DS0477EJ0115 Rev.1.15

Page 71 of 112

Nov 28, 2025

3.5.15

Renesas Serial Peripheral Interface (RSPI) Access Timing

Conditions:

VOH = VDD18 × 0.5, VOL = VDD18 × 0.5, C = 30 pF (1.8 V)

VOH = VDD33 × 0.5, VOL = VDD33 × 0.5, C = 30 pF (3.3 V)

Drive strength: ×6

Table 3.20

RSPI Timing (1/2)

Parameter

Symbol

Min.*1

Max.*1

Unit

Figure

RSPCK clock cycle

Master

tSPcyc

4096

tSPIcyc

Figure 3.38

Slave

4 / 8*6

4096

tSPIcyc

RSPCK clock high-level pulse

width

Master

tSPCKWH

(tSPcyc − tSPCKr − tSPCKf)/2 − 2.5

—

Slave

—

tSPIcyc

RSPCK clock low-level pulse

width

Master

tSPCKWL

(tSPcyc − tSPCKr − tSPCKf)/2 − 2.5

—

Slave

—

tSPIcyc

RSPCK clock rise/fall time

Output

tSPCKr,

tSPCKf

—

3*5

Input

—

3*5

Data input setup time

Master

tSU

—

Figure 3.39 to

Figure 3.45

Slave

—

Data input hold time

Master

—

Slave

—

SSL setup time

Master

tLEAD

N × tSPcyc − 3*2

N × tSPcyc + 3*2

Figure 3.39 to

Figure 3.42

Slave

—

tSPIcyc

SSL hold time

Master

tLAG

N × tSPcyc − 3*3

N × tSPcyc + 3*3

Slave

—

tSPIcyc

Continuous transmission

delay

Master

tTD

tSPcyc + 2 × tSPIcyc

8 × tSPcyc + 2 ×

tSPIcyc

Slave

tSPcyc + 5 × tSPIcyc

—

TI-SSP SS input setup time

tTISS

—

Figure 3.43 to

Figure 3.45

TI-SSP SS input hold time

tTISH

—

TI-SSP next access time

tTIND

M*4

—

tSPIcyc

TI-SSP Master SS output

delay

tTISSOD

−3

TI-SSP Master OE delay 1

tTIMOED1

—

TI-SSP Master OE delay 2

tTIMOED2

—

TI-SSP Slave OE delay 1

tTISOED1

—

7.5 / 10*6

TI-SSP Slave OE delay 2

tTISOED2

—

7.5 / 10*6

SSL Activation to Data Output

Delay

tOD1

—

Figure 3.39

Data output delay time

Master

tOD

—

Figure 3.39 to

Figure 3.45

Slave

—

7.5 / 10*6

Data output hold time

Master

tOH

−3

—

Slave

—

MOSI, MISO rise/fall time

Output

tDr, tDf

—

3*5

Input

—

μs

SSL rise/fall time

Output

tSSLr, tSSLf

—

3*5

Figure 3.39,

Figure 3.40

Input

—

μs

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