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RZ/G3E Datasheet(PDF) 16 Page - Renesas Technology Corp |
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RZ/G3E Datasheet(HTML) 16 Page - Renesas Technology Corp |
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16 / 112 page  RZ/G3E Group 1. Overview R01DS0477EJ0115 Rev.1.15 Page 16 of 112 Nov 28, 2025 1.2 Block Diagram Core 0 Shared L3$ 1024KB Cortex-A55 quad core Cortex-M33 I$ 32KB Neon D$ 32KB Crypto Core 1 I$ 32KB Neon D$ 32KB Crypto CPG PLL/SSCG xSPI LCD Controller Camera Interface Display Interface CRU VSPD FCPVD Audio VCD External Memory Storage and Network WDT0 (1ch) CMTW0 to 3 (4ch) RIIC8 (1ch) SCIF (1ch) RSPI (3ch) Analog Security Timer Peripheral MIPI CSI-2 MIPI DSI USB21 Host USB20 Host / Function GBETH0 CANFD (6ch) SRC SSIU (10ch) ADC (8ch) Renesas Secure IP OTP PFC Video Processing GIC System SRAM1 256KB Network External Memory Internal Memory MHU Multi CPU System Cortex-M33 Core 2 I$ 32KB Neon D$ 32KB Crypto Core 3 I$ 32KB Neon D$ 32KB Crypto Frame Data Processor FDP USB30 Host GBETH1 PCIE0 SRAM0 256KB ICU Audio PDM0 (3ch) PDM1 (3ch) GTM0 to 1 (2ch) RTC (1ch) Graphics Processing GE3D [Mali-G52] WDT2 to 3 (2ch) CMTW4 to 7 (4ch) Timer Peripheral GTM4 to 7 (4ch) GPT (2ch) I3C (1ch) RSCI (10ch) CRC System NPU [Ethos-U55] (Option) Analog TSU WDT1 (1ch) Timer GTM2 to 3 (2ch) SPDIF (3ch) RIIC0 to 7 (8ch) Peripheral DMAC1 (16ch) DMAC3 (16ch) DMAC4 (16ch) External Memory SD0 (SD/eMMC) SD2 SD1 (SD/eMMC) DMAC0 (16ch) TZC DMAC2 (16ch) TZC (DDR_0) TZC (DDR_1) ACPU Bus PMU ADMAC ADG SCU CST Debug Interface Micro Neural network Processing Unit Port 1 Port 0 Port 2 Port 3 Port 4 DDR (LPDDR4/4X) Internal Memory Video Signal Processor VSP LCD Controller VSPD FCPVD LVDS LVDS Parallel Figure 1.1 Block Diagram |
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