HD64F36049 datasheet(336/562 Pages) RENESAS

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Section 17 Serial Communication Interface 3 (SCI3)

Rev. 3.00 Mar. 15, 2006 Page 304 of 526

REJ09B0060-0300

17.3.3

Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first

transfers transmit data from TDR to TSR automatically, then sends the data that starts from the

LSB to the TXD pin

. TSR cannot be directly accessed by the CPU.

17.3.4

Transmit Data Register (TDR)

TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is

empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-

buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit

data has already been written to TDR during transmission of one-frame data, the SCI3 transfers

the written data to TSR to continue transmission. To achieve reliable serial transmission, write

transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is

initialized to H'FF.

17.3.5

Serial Mode Register (SMR)

SMR is used to set the SCI3's serial transfer format and select the baud rate generator clock

source.

Bit

Bit Name

Initial

Value

R/W

Description

COM

R/W

Communication Mode

0: Asynchronous mode

1: Clocked synchronous mode

CHR

R/W

Character Length (enabled only in asynchronous mode)

0: Selects 8 bits as the data length.

1: Selects 7 bits as the data length.

R/W

Parity Enable (enabled only in asynchronous mode)

When this bit is set to 1, the parity bit is added to

transmit data before transmission, and the parity bit is

checked in reception.

R/W

Parity Mode (enabled only when the PE bit is 1 in

asynchronous mode)

0: Selects even parity.

1: Selects odd parity.

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