HD64F36049 datasheet(338/562 Pages) RENESAS

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Section 17 Serial Communication Interface 3 (SCI3)

Rev. 3.00 Mar. 15, 2006 Page 306 of 526

REJ09B0060-0300

17.3.6

Serial Control Register 3 (SCR3)

SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is

also used to select the transfer clock source. For details on interrupt requests, see section 17.7,

Interrupt Requests.

Bit

Bit Name

Initial

Value

R/W

Description

TIE

R/W

Transmit Interrupt Enable

When this bit is set to 1, the TXI interrupt request is

enabled.

RIE

R/W

Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt requests

are enabled.

R/W

Transmit Enable

When this bit s set to 1, transmission is enabled.

R/W

Receive Enable

When this bit is set to 1, reception is enabled.

MPIE

R/W

Multiprocessor Interrupt Enable (enabled only when the

MP bit in SMR is 1 in asynchronous mode)

When this bit is set to 1, receive data in which the

multiprocessor bit is 0 is skipped, and setting of the

RDRF, FER, and OER status flags in SSR is disabled.

On receiving data in which the multiprocessor bit is 1,

this bit is automatically cleared and normal reception is

resumed. For details, see section 17.6, Multiprocessor

Communication Function.

TEIE

R/W

Transmit End Interrupt Enable

When this bit is set to 1, TEI interrupt request is

enabled.

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