HD64F36049 datasheet(117/562 Pages) RENESAS

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Section 6 Power-Down Modes

Rev. 3.00 Mar. 15, 2006 Page 85 of 526

REJ09B0060-0300

6.2.3

Subsleep Mode

In subsleep mode, operation of the CPU and on-chip peripheral modules other than RTC is halted.

As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and

some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as

before the transition.

Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared

and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1

or the requested interrupt is disabled in the interrupt enable register. After subsleep mode is

cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is

made to subactive mode when the bit is 1. After the time set in bits STS2 to STS0 in SYSCR1 has

elapsed, a transition is made to active mode.

When the

RES pin goes low, the system clock pulse generator starts. Since system clock signals

are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the

RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator

output has stabilized, the CPU starts reset exception handling if the

RES pin is driven high.

6.2.4

Subactive Mode

The operating frequency of subactive mode is selected from

W/2, φW/4, and φW/8 by the SA1 and

SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to

the frequency which is set before the execution.

When the SLEEP instruction is executed in subactive mode, a transition to sleep mode, subsleep

mode, standby mode, active mode, or subactive mode is made, depending on the combination of