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SH7101 Datasheet(PDF) 250 Page - Renesas Technology Corp

Part # SH7101
Description  32-Bit RISC Microcomputer
PDF  486 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7101 Datasheet(HTML) 250 Page - Renesas Technology Corp

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8. Multi-Function Timer Pulse Unit (MTU)
Rev.2.00 Sep. 27, 2007 Page 216 of 448
REJ09B0394-0200
8.7.15
Overflow Flags in Reset Sync PWM Mode
When set to reset sync PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of
TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3
setting.
In reset sync PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying
TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF,
then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this
point, TSR's overflow flag TCFV bit is not set.
Figure 8.81 shows a TCFV bit operation example in reset sync PWM mode with a set value for
cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without
synchronous setting for the counter clear source.
TGRA_3
(H'FFFF)
H'0000
TCFV_3
TCFV_4
TCNT_3 = TCNT_4
Counter cleared by compare match 3A
Not set
Not set
Figure 8.81 Reset Sync PWM Mode Overflow Flag



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