32182 datasheet(126/755 Pages) RENESAS

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5-9

INTERRUPT CONTROLLER (ICU)

32182 Group User’s Manual (Rev.1.0)

5.2 ICU Related Registers

(1) IREQ (Interrupt Request) bit (Bit 3 or 11)

When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Re-

quest) bit is set to "1".

This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for

level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt re-

quest generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not

cleared in the case of level-recognized interrupt request).

If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in

software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the

same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority.

Note: • External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External

Interrupt (EI) to the CPU core can only be deasserted by the following operation:

(1) Reset

(2) IVECT register read

(3) Write to the IMASK register

Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type)

Interrupt request from

each internal peripheral I/O

Interrupt enabled

ILEVEL

(levels 0-7)

Data bus

Bits 5-7 or bits 13-15

F/F

Set

Set/clear

IREQ

Interrupt priority

resolving circuit

F/F

Reset

IVECT read

IMASK write

Clear

To the CPU core

Bit 3 or 11

Set

Interrupt request from each

group internal peripheral I/O

Interrupt enabled

b3, b11

Data bus

b5-b7, b13-b15

Read

IREQ

Read-only circuit

ILEVEL

(levels 0-7)

Group interrupt

Interrupt priority

resolving circuit

F/F

Clear

To the CPU core

Set

Reset

IVECT read

IMASK write

Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type)

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