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5-10

INTERRUPT CONTROLLER (ICU)

32182 Group User’s Manual (Rev.1.0)

5.2 ICU Related Registers

(2) ILEVEL (Interrupt Priority Level) (Bits 5–7 or bits 13–15)

These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to ‘111’

to disable or any value ‘000’ through ‘110’ to enable the interrupt from some internal peripheral I/O.

When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt

sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether

to forward an EI request to the CPU or keep the interrupt request pending.

The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts

are accepted.

Table 5.2.1 ILEVEL Settings and Accepted IMASK Values

ILEVEL values set

IMASK values at which interrupts are accepted

0 (ILEVEL = "000")

Accepted when IMASK is 1–7

1 (ILEVEL = "001")

Accepted when IMASK is 2–7

2 (ILEVEL = "010")

Accepted when IMASK is 3–7

3 (ILEVEL = "011")

Accepted when IMASK is 4–7

4 (ILEVEL = "100")

Accepted when IMASK is 5–7

5 (ILEVEL = "101")

Accepted when IMASK is 6–7

6 (ILEVEL = "110")

Accepted when IMASK is 7

7 (ILEVEL = "111")

Not accepted (interrupts disabled)

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