7480 datasheet(150/337 Pages) RENESAS

150 / 337 page

7480 Group and 7481 Group User's Manual

1-133

HARDWARE

1.14 Serial I/O

Receive data transfer

Serial I/O status register

Address 00E116

Receive shift register

P14/RxD

D3 D2

Receive shift register

P14/RxD

D7 D6 D5 D4 D3 D2

Synchronous clock

Receive shift register

Receive buffer register

Address 00E016

RxD (Noise)

RxD (ST)

HIGH is identified as noise.

LOW is identified as a start bit.

Synchronous clock

RxD (SP)

Stop bit detected

b6 b5 b4 b3

0 000

Receive buffer full flag

∗ : b3

Overrun error flag (OE); set to ‘1’ when overrun error occurs.

Parity error flag (PE); set to ‘1’ when parity error occurs.

Framing error flag (FE); set to ‘1’ when framing error occurs.

Summing error flag (SE); set to ‘1’ when OE U PE U FE = 1.

Synchronous clock

∗∗∗ ∗

• • •

Figure 1.14.20 Receive Timing Example in UART

Figure 1.14.19 Receive Operation of UART

Synchronous clock

RxD pin

Receive buffer full flag

Serial I/O receive interrupt

request bit

• Example of 1ST-7DATA-1PA-1SP

Receive buffer register

read signal

Test whether a start bit or not

Reading to the receive shift register

: Clearing by writing ‘0’ to the serial I/O receive interrupt request bit or

accepting a serial I/O receive interrupt request.

7480 Datasheet(PDF) 150 Page - Renesas Technology Corp

7480 Datasheet(HTML) 150 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL