7480 datasheet(149/337 Pages) RENESAS

149 / 337 page

7480 Group and 7481 Group User's Manual

1-132

HARDWARE

(3)

Operations of UART Reception

Receive Operation

When a falling edge of the RxD pin input is detected, this input level to the RxD pin is identified

according to the subsequent rising edge of the synchronous clock as follows:

• As the start bit when the level is LOW.

• As noise when the level is HIGH. In this case, the CPU suspends the receive operation and

enters the waiting state for the next start bit.

Synchronized with the rising edge of the synchronous clock, transmitted data is received on the

RxD pin by the bit and stored in the most significant bit (MSB) of the receive shift register. Every

time a data bit is received, the contents of the receive shift register are shifted by one bit to the

low-order direction.

The receive shift operation of ‘Receive Operation ’ is performed ‘n’ times (‘n’: the number of bits

set by the character length selection bit of the UART control register), and the received data is

stored completely in the receive shift register (Note 1).

The received data stored completely in the receive shift register is transferred to the receive buffer

The parity bit and the stop bit are input to the RxD pin synchronized with rising edges of the

synchronous clock. When the last stop bit (the HIGH level) is input to the RxD pin, the receive

buffer full flag of the serial I/O status register is set to ‘1’ at the subsequent falling edge of the

synchronous clock (Note 2).

At this time, error flags are checked.

Notes 1: When the character length selection bit is ‘1’ (7 bits wide), the MSB of the receive buffer

2: If the next data is stored completely in the receive shift register before the data transferred

from the receive shift register to the receive buffer register is read through (the receive

buffer full flag is ‘1’), the overrun error is generated. At this time, the overrun error flag and

the summing error flag of the serial I/O status register is set to ‘1’. Refer to (5) Notes on

Usage of UART.

When the receive buffer register is read, the receive buffer full flag is cleared to ‘0’.

Serial I/O Receive Interrupt

When the receive buffer full flag goes to ‘1’ (‘Receive Operation ’), the serial I/O receive interrupt

request bit of interrupt request register 1 is set to ‘1’; then the interrupt request is generated.

Figure 1.14.19 shows the receive operation of UART and Figure 1.14.20 shows a receive timing

example in UART.

1.14 Serial I/O

7480 Datasheet(PDF) 149 Page - Renesas Technology Corp