7480 datasheet(147/337 Pages) RENESAS

147 / 337 page

7480 Group and 7481 Group User's Manual

1-130

HARDWARE

(2)

Operations of UART Transmission

Transmit Operation

When transmit data is written to the transmit buffer register, the transmit buffer empty flag of the

serial I/O status register is cleared to ‘0’.

The transmit data written to the transmit buffer register is transferred to the transmit shift register.

When the data transfer to the transmit shift register is completed, the transmit buffer empty flag

goes to ‘1’ (Note 1).

Synchronized with a falling edge of the synchronous clock, the start bit (the LOW level) is output

from the TxD pin.

Synchronized with the next falling edge of the synchronous clock, the least significant bit (LSB)

of the transmit data transferred to the transmit shift register is output from the TxD pin. At this time,

the contents of the transmit shift register are shifted to the low-order direction by one bit, and the

serial I/O transmit shift completion flag is cleared to ‘0’.

By repeating the shift operation of ‘Transmit Operation ’ ‘n’ times (‘n’: the number of bits set by

the character length selection bit of the UART control register), the transmit data is output from

the TxD pin by the bit from the LSB.

After the transmit data is output, the parity bit, and then the stop bit (the HIGH level), are output

from the TxD pin synchronized with falling edges of the synchronous clock. The parity bit and the

stop bit are generated and output automatically, according to the setting of the parity enable bit,

the parity selection bit, and the stop bit length selection bit of the UART control register.

When the last stop bit of the transfer format is output, the transmit shift completion flag is set to

‘1’ at the next rising edge of the synchronous clock (Note 2).

Notes 1: When the transmit buffer empty flag is ‘1’, the next transmit data can be written to the

transmit buffer register.

2: The supply of the synchronous clock pulse to the transmit shift register stops automatically

upon transmit completion when the BRG output/16 is selected as the synchronous clock.

However, when the next transmit data is written to the transmit buffer register during the

‘0’ state of the transmit shift completion flag, the supply of the synchronous clock pulse

continues, and data is successively transmitted.

Serial I/O Transmit Interrupt

In the following cases, the serial I/O transmit interrupt request bit of interrupt request register 1 is

set to ‘1’; then the interrupt request is generated:

• When the transmit interrupt source selection bit is ‘0’, and the data written to the transmit buffer

• When the transmit interrupt source selection bit is ‘1’, and the shift operation of the transmit shift

Figure 1.14.17 shows the transmit operation of UART, and Figure 1.14.18 shows a transmit timing

example in UART.

1.14 Serial I/O

7480 Datasheet(PDF) 147 Page - Renesas Technology Corp