7480 datasheet(148/337 Pages) RENESAS

148 / 337 page

7480 Group and 7481 Group User's Manual

1-131

HARDWARE

Figure 1.14.17 Transmit Operation of UART

1.14 Serial I/O

Figure 1.14.18 Transmit Timing example in UART

D7 D6 D5 D4 D3 D2 D1

P15/TxD

D7 D6 D5 D4 D3 D2 D1

P15/TxD

D7 D6 D5 D4 D3 D2 D1

P15/TxD

D0 ST

Transmit buffer register

Address 00E016

Serial I/O status register

Address 00E116

Writing transmit data

Transmit shift register

Transferring transmit data

Transmit buffer register

Address 00E016

Synchronous clock

Transmit shift register

Transmit buffer empty flag

Synchronous clock

Transmit shift register

Synchronous clock

Transmit shift completion flag

Transmit buffer empty flag

Data bus

Serial I/O status register

Address 00E116

Serial I/O status register

Address 00E116

Serial I/O status register

Address 00E116

Synchronous clock

Transmit shift register

Synchronous clock

TxD pin

Transmit buffer empty flag

Transmit shift completion flag

Serial I/O transmit

interrupt request bit

Transmit buffer register

write signal

(Note 2)

(Note 1)

• Example of 1ST-8DATA-1SP

Notes 1: When the transmit interrupt source selection bit is ‘0’ (transmit buffer is emptied).

2: When the transmit interrupt source selection bit is ‘1’ (transmit shift operation is completed).

: Clearing by writing ‘0’ to the serial I/O transmit interrupt request bit or

accepting a serial I/O transmit interrupt request.

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