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82G33 Datasheet(PDF) 276 Page - Intel Corporation |
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82G33 Datasheet(HTML) 276 Page - Intel Corporation |
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276 / 437 page ![]() Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 276 Datasheet 8.2.15 MINGNT—Minimum Grant B/D/F/Type: 0/2/1/PCI Address Offset: 3Eh Default Value: 00h Access: RO Size: 8 bits Bit Access & Default Description 7:0 RO 00h Minimum Grant Value (MGV): The IGD does not burst as a PCI compliant master. 8.2.16 MAXLAT—Maximum Latency B/D/F/Type: 0/2/1/PCI Address Offset: 3Fh Default Value: 00h Access: RO Size: 8 bits Bit Access & Default Description 7:0 RO 00h Maximum Latency Value (MLV): The IGD has no specific requirements for how often it needs to access the PCI bus. 8.2.17 CAPID0—Mirror of Dev0 Capability Identifier B/D/F/Type: 0/2/1/PCI Address Offset: 40–50h Default Value: 00000000000000000100000000010B0009h Access: RO Size: 136 bits BIOS Optimal Default 000000000000h This register control of bits in this register are only required for customer visible SKU differentiation. Bit Access & Default Description 7:0 RO 09h Capability Identifier (CAP_ID): This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers. |
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