82G33 datasheet(273/437 Pages) INTEL

273 / 437 page

Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

Datasheet

273

8.2.9

HDR2—Header Type

B/D/F/Type:

0/2/1/PCI

Address Offset:

0Eh

Default Value:

80h

Access:

Size:

8 bits

This register contains the Header Type of the IGD.

Bit

Access &

Default

Description

Multi Function Status (MFUNC): Indicates if the device is a Multi-

Function Device. The Value of this register is determined by Device 0,

offset 54h, DEVEN[4]. If Device 0 DEVEN[4] is set, the MFUNC bit is

also set.

6:0

00h

Header Code (H): This is a 7-bit value that indicates the Header Code

for the IGD. This code has the value 00h, indicating a type 0

configuration space format.

8.2.10

MMADR—Memory Mapped Range Address

B/D/F/Type:

0/2/1/PCI

Address Offset:

10–13h

Default Value:

00000000h

Access:

RW, RO

Size:

32 bits

This register requests allocation for the IGD registers and instruction ports. The

allocation is for 512 KB and the base address is defined by bits 31:19.

Bit

Access &

Default

Description

31:19

0000h

Memory Base Address (MBA): Set by the OS, these bits correspond

to address signals 31:19.

18:4

0000h

Address Mask (ADMSK): Hardwired to 0s to indicate 512 KB address

range.

Prefetchable Memory (PREFMEM): Hardwired to 0 to prevent

prefetching.

2:1

00b

Memory Type (MEMTYP): Hardwired to 0s to indicate 32-bit address.

Memory / IO Space (MIOS): Hardwired to 0 to indicate memory

space.

82G33 Datasheet(PDF) 273 Page - Intel Corporation

82G33 Datasheet(HTML) 273 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL