82G33 datasheet(269/437 Pages) INTEL

269 / 437 page

Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

Datasheet

269

8.2.3

PCICMD2—PCI Command

B/D/F/Type:

0/2/1/PCI

Address Offset:

04–05h

Default Value:

0000h

Access:

RO, RW

Size:

16 bits

This 16-bit register provides basic control over the IGD's ability to respond to PCI

cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master

accesses to main memory.

Bit

Access &

Default

Description

15:10

Reserved

Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.

SERR Enable (SERRE): Not Implemented. Hardwired to 0.

Address/Data Stepping Enable (ADSTEP): Not Implemented.

Hardwired to 0.

Parity Error Enable (PERRE): Not Implemented. Hardwired to 0.

Since the IGD belongs to the category of devices that does not corrupt

programs or data in system memory or hard drives, the IGD ignores

any parity error that it detects and continues with normal operation.

VGA Palette Snoop Enable (VGASNOOP): This bit is hardwired to 0

to disable snooping.

Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The

IGD does not support memory write and invalidate commands.

Special Cycle Enable (SCE): This bit is hardwired to 0. The IGD

ignores Special cycles.

Bus Master Enable (BME):

0 = Disable IGD bus mastering.

1 = Enable the IGD to function as a PCI compliant master.

Memory Access Enable (MAE): This bit controls the IGD's response

to memory space accesses.

0 = Disable.

1 = Enable.

I/O Access Enable (IOAE): This bit controls the IGD's response to

I/O space accesses.

0 = Disable.

1 = Enable.

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