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82G33 Datasheet(PDF) 266 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 266 Page - Intel Corporation

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Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
266
Datasheet
8.2
IGD Configuration Register Details (D2:F1)
The Integrated Graphics Device registers are located in Device 2 (D2), Function 0 (F0)
and Function 1 (F1). This section provides the descriptions for the D2:F1 registers.
Table 8-2 provides an address map of the D2:F1registers listed in ascending order by
address offset. Detailed bit descriptions follow the table.
Table 8-2. Integrated Graphics Device Register Address Map (D2:F1)
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
00–01h
VID2
Vendor Identification
8086h
RO
02–03h
DID2
Device Identification
29C3h
RO
04–05h
PCICMD2
PCI Command
0000h
RO, RW
06–07h
PCISTS2
PCI Status
0090h
RO
08h
RID2
Revision Identification
00h
RO
09–0Bh
CC
Class Code Register
038000h
RO
0Ch
CLS
Cache Line Size
00h
RO
0Dh
MLT2
Master Latency Timer
00h
RO
0Eh
HDR2
Header Type
80h
RO
10–13h
MMADR
Memory Mapped Range Address
00000000h
RW, RO
2C–2Dh
SVID2
Subsystem Vendor Identification
0000h
RO
2E–2Fh
SID2
Subsystem Identification
0000h
RO
30–33h
ROMADR
Video BIOS ROM Base Address
00000000h
RO
34h
CAPPOINT
Capabilities Pointer
D0h
RO
3Eh
MINGNT
Minimum Grant
00h
RO
3Fh
MAXLAT
Maximum Latency
00h
RO
40–50h
CAPID0
Mirror of Dev0 Capability Identifier
0000000000
0000000100
000000010
B0009h
RO
52–53h
MGGC
Mirror of Dev 0 GMCH Graphics
Control Register
0030h
RO
54–57h
DEVEN
Device Enable
000003DBh
RO
58–5Bh
SSRW
Mirror of Fun 0 Software Scratch
Read Write
00000000h
RO
5C–5Fh
BSM
Mirror of Func0 Base of Stolen
Memory
07800000h
RO
60–61h
HSRW
Mirror of Dev2 Func0 Hardware
Scratch Read Write
0000h
RO



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