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82G33 Datasheet(PDF) 267 Page - Intel Corporation |
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82G33 Datasheet(HTML) 267 Page - Intel Corporation |
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267 / 437 page ![]() Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Datasheet 267 Address Offset Register Symbol Register Name Default Value Access 62h MSAC Mirror of Dev2 Func0 Multi Size Aperture Control 02h RO C0h GDRST Mirror of Dev2 Func0 Graphics Reset 00h RO C1–C3h MI_GFX_CG_ DIS Mirror of Fun 0 MI GFX Unit Level Clock Ungating 000000h RO C4–C7h RSVD Reserved 00000000h RO C8h RSVD Reserved 00h RO CA–CBh RSVD Reserved 0000h RO CC–CDh GCDGMBUS Mirror of Dev2 Func0 Graphics Clock Frequency Register for GMBUS unit 0000h RO D0–D1h PMCAPID Mirror of Fun 0 Power Management Capabilities ID 0001h RO D2–D3h PMCAP Mirror of Fun 0 Power Management Capabilities 0022h RO D4–D5h PMCS Power Management Control/Status 0000h RO, RW D8–DBh RSVD Reserved 00000000h RO E0–E1h SWSMI Mirror of Func0 Software SMI 0000h RO E4–E7h ASLE Mirror of Dev2 Func0 System Display Event Register 00000000h RO F0–F3h GCFGC Mirror of Dev2 Func0 Graphics Clock Frequency and Gating Control 00000000h RO/P, RO F4–F7h RSVD Mirror of Fun 0 Reserved for LBB- Legacy Backlight Brightness 00000000h RO FC–FFh ASLS ASL Storage 00000000h RW |
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