82G33 datasheet(263/437 Pages) INTEL

263 / 437 page

Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

Datasheet

263

8.1.30

PMCAPID—Power Management Capabilities ID

B/D/F/Type:

0/2/0/PCI

Address Offset:

D0–D1h

Default Value:

0001h

Access:

RWO, RO

Size:

16 bits

Bit

Access &

Default

Description

15:8

RWO

00h

Next Capability Pointer (NEXT_PTR): This field contains a

pointer to the next item in the capabilities list. BIOS is responsible for

writing this to the FLR Capability when applicable.

7:0

01h

Capability Identifier (CAP_ID): SIG defines this ID is 01h for

power management.

8.1.31

PMCAP—Power Management Capabilities

B/D/F/Type:

0/2/0/PCI

Address Offset:

D2–D3h

Default Value:

0022h

Access:

Size:

16 bits

This register is a Mirror of Function 0 with the same read/write attributes. The

hardware implements a single physical register common to both functions 0 and 1.

Bit

Access &

Default

Description

15:11

00h

PME Support (PMES): This field indicates the power states in which

the IGD may assert PME#. Hardwired to 0 to indicate that the IGD

does not assert the PME# signal.

D2 Support (D2): The D2 power management state is not supported.

This bit is hardwired to 0.

D1 Support (D1): Hardwired to 0 to indicate that the D1 power

management state is not supported.

8:6

000b

Reserved

Device Specific Initialization (DSI): Hardwired to 1 to indicate that

special initialization of the IGD is required before generic class device

driver is to use it.

Reserved

PME Clock (PMECLK): Hardwired to 0 to indicate IGD does not

support PME# generation.

2:0

010b

Version (VER): Hardwired to 010b to indicate that there are 4 bytes

of power management registers implemented and that this device

complies with revision 1.1 of the PCI Power Management Interface

Specification.

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