82G33 datasheet(260/437 Pages) INTEL

260 / 437 page

Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

260

Datasheet

8.1.26

MC—Message Control

B/D/F/Type:

0/2/0/PCI

Address Offset:

92–93h

Default Value:

0000h

Access:

RO, RW

Size:

16 bits

System software can modify bits in this register, but the device is prohibited from

doing so. If the device writes the same message multiple times, only one of those

messages is ensured to be serviced. If all of them must be serviced, the device must

not generate the same message again until the driver services the earlier one.

Bit

Access &

Default

Description

15:8

00h

Reserved

64 Bit Capable (64BCAP): Hardwired to 0 to indicate that the

function does not implement the upper 32 bits of the Message address

This may need to change in future implementations when addressable

system memory exceeds the 32b / 4 GB limit.

6:4

000b

Multiple Message Enable (MME): System software programs this

field to indicate the actual number of messages allocated to this

device. This number will be equal to or less than the number actually

requested.

The encoding is the same as for the MMC field (Bits 3:1).

3:1

000b

Multiple Message Capable (MMC): System Software reads this field

to determine the number of messages being requested by this device.

000 = 1

All of the following are reserved in this implementation

001 = 2

010 = 4

011 = 8

100 = 16

101 = 32

110 = Reserved

111 = Reserved

MSI Enable (MSIEN): This bit controls the ability of this device to

generate MSIs.

82G33 Datasheet(PDF) 260 Page - Intel Corporation

82G33 Datasheet(HTML) 260 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL