82G33 datasheet(258/437 Pages) INTEL

258 / 437 page

Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

258

Datasheet

Bit

Access &

Default

Description

EP Function 0 (D3F0EN):

0 = Bus 0, Device 3, Function 0 is disabled and hidden

1 = Bus 0, Device 3, Function 0 is enabled and visible. If this GMCH

does not have ME capability (CAPID0[??] = 1), then Device 3,

Function 0 is disabled and hidden independent of the state of this

bit.

Reserved

Internal Graphics Engine Function 1 (D2F1EN):

0 = Bus 0, Device 2, Function 1 is disabled and hidden

1 = Bus 0, Device 2, Function 1 is enabled and visible

If Device 2, Function 0 is disabled and hidden, then Device 2, Function

1 is also disabled and hidden independent of the state of this bit.

If this component is not capable of Dual Independent Display

(CAPID0[78] = 1), then this bit is hardwired to 0b to hide Device 2,

Function 1.

Internal Graphics Engine Function 0 (D2F0EN):

0 = Bus 0, Device 2, Function 0 is disabled and hidden

1 = Bus 0, Device 2, Function 0 is enabled and visible

If this GMCH does not have internal graphics capability

(CAPID0[46] = 1), then Device 2, Function 0 is disabled and hidden

independent of the state of this bit.

Reserved

PCI Express Port (D1EN):

0 = Bus 0, Device 1, Function 0 is disabled and hidden.

1 = Bus 0, Device 1, Function 0 is enabled and visible.

Default value is determined by the device capabilities (see CAPID0

[44]), SDVO Presence hardware strap and the SDVO/PCIe Concurrent

hardware strap. Device 1 is Disabled on Reset if the SDVO Presence

strap was sampled high, and the SDVO/PCIe Concurrent strap was

sampled low at the last assertion of PWROK, and is enabled by default

otherwise.

Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be

disabled and is therefore hardwired to 1.

82G33 Datasheet(PDF) 258 Page - Intel Corporation