82G33 datasheet(257/437 Pages) INTEL

257 / 437 page

Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

Datasheet

257

8.1.22

DEVEN—Device Enable

B/D/F/Type:

0/2/0/PCI

Address Offset:

54–57h

Default Value:

000003DBh

Access:

Size:

32 bits

This register allows for enabling/disabling of PCI devices and functions that are within

the GMCH. The table below the bit definitions describes the behavior of all

combinations of transactions to devices controlled by this register. All the bits in this

Bit

Access &

Default

Description

31:15

00000h

Reserved

Chap Enable (D7EN):

0 = Bus 0, Device 7 is disabled and not visible.

1 = Bus 0, Device 7 is enabled and visible. Non-production BIOS code

should provide a setup option to enable Bus 0, Device 7. When

enabled, Bus 0, Device 7 must be initialized in accordance to

standard PCI device initialization procedures.

13:10

Reserved

EP Function 3 (D3F3EN):

0 = Bus 0, Device 3, Function 3 is disabled and hidden

1 = Bus 0, Device 3, Function 3 is enabled and visible If Device 3,

Function 0 is disabled and hidden, then Device 3, Function 3 is also

disabled and hidden independent of the state of this bit.

EP Function 2 (D3F2EN):

0 = Bus 0, Device 3, Function 2 is disabled and hidden

1 = Bus 0, Device 3, Function 2 is enabled and visible If Device 3,

Function 0 is disabled and hidden, then Device 3, Function 2 is also

disabled and hidden independent of the state of this bit.

EP Function 1 (D3F1EN):

0 = Bus 0, Device 3, Function 1 is disabled and hidden

1 = Bus 0, Device 3, Function 1 is enabled and visible. If this GMCH

does not have ME capability (CAPID0[??] = 1), then Device 3,

Function 1 is disabled and hidden independent of the state of this

bit.

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