82G33 datasheet(261/437 Pages) INTEL

261 / 437 page

Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

Datasheet

261

8.1.27

MA—Message Address

B/D/F/Type:

0/2/0/PCI

Address Offset:

94–97h

Default Value:

00000000h

Access:

RW, RO

Size:

32 bits

Bit

Access &

Default

Description

31:2

00000000h

Message Address (MESSADD): Used by system software to assign

an MSI address to the device.

The device handles an MSI by writing the padded contents of the MD

1:0

00b

Force DWord Align (FDWORD): Hardwired to 0 so that addresses

assigned by system software are always aligned on a DWord address

boundary.

8.1.28

MD—Message Data

B/D/F/Type:

0/2/0/PCI

Address Offset:

98–99h

Default Value:

0000h

Access:

Size:

16 bits

Bit

Access &

Default

Description

15:0

0000h

Message Data (MESSDATA): Base message data pattern assigned

by system software and used to handle an MSI from the device.

When the device must generate an interrupt request, it writes a 32-bit

value to the memory address specified in the MA register. The upper

16 bits are always set to 0. The lower 16 bits are supplied by this

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