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82G33 Datasheet(PDF) 265 Page - Intel Corporation |
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82G33 Datasheet(HTML) 265 Page - Intel Corporation |
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265 / 437 page ![]() Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) Datasheet 265 8.1.33 SWSMI—Software SMI B/D/F/Type: 0/2/0/PCI Address Offset: E0–E1h Default Value: 0000h Access: RW Size: 16 bits As long as there is the potential that DVO port legacy drivers exist which expect this register at this address, D2, F0 address E0h–E1h must be reserved for this register. Bit Access & Default Description 15:8 RW 00h Software Scratch Bits (SWSB): 7:1 RW 00h Software Flag (SWF): Used to indicate caller and SMI function desired, as well as return result. 0 RW 0b GMCH Software SMI Event (GSSMIE): When Set this bit will trigger an SMI. Software must write a "0" to clear this bit. |
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