82G33 datasheet(262/437 Pages) INTEL

262 / 437 page

Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

262

Datasheet

8.1.29

GDRST—Graphics Debug Reset

B/D/F/Type:

0/2/0/PCI

Address Offset:

C0h

Default Value:

00h

Access:

RO, RW

Size:

8 bits

Bit

Access &

Default

Description

7:4

Reserved

3:2

00b

Graphics Reset Domain (GRDOM):

00 = Full Graphics Reset will be performed (both render and display

clock domain resets asserted

01 = Reserved (Invalid Programming)

10 = Reserved (Invalid Programming)

11 = Reserved (Invalid Programming)

Reserved

Graphics Reset Enable (GR): Setting this bit asserts graphics-only

reset. The clock domains to be reset are determined by GRDOM.

Hardware resets this bit when the reset is complete. Setting this bit

without waiting for it to clear, is undefined behavior. Once this bit is

set to a 1, all GFX core MMIO registers are returned to power on

default state. All Ring buffer pointers are reset, command stream

fetches are dropped and ongoing render pipeline processing is halted,

state machines and State Variables returned to power on default state.

If the Display is reset, all display engines are halted (garbage on

screen). VGA memory is not available, Store DWords and interrupts

are not assured to be completed. Device 2 I/O registers are not

available.

When issuing the graphics reset, disable the cursor, display, and

overlay engines using the MMIO registers. Wait 1 us. Issue the

graphics reset by setting this bit to 1.

Device 2 Configuration registers continue to be available while graphics

reset is asserted.

This bit is hardware auto-clear.

82G33 Datasheet(PDF) 262 Page - Intel Corporation

82G33 Datasheet(HTML) 262 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL