82G33 datasheet(264/437 Pages) INTEL

264 / 437 page

Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

264

Datasheet

8.1.32

PMCS—Power Management Control/Status

B/D/F/Type:

0/2/0/PCI

Address Offset:

D4–D5h

Default Value:

0000h

Access:

RO, RW

Size:

16 bits

Bit

Access &

Default

Description

PME Status (PMESTS): This bit is 0 to indicate that IGD does not

support PME# generation from D3 (cold).

14:13

00b

Data Scale (DSCALE): The IGD does not support data register. This

bit always returns 00 when read, write operations have no effect.

12:9

Data Select (DSEL): The IGD does not support data register. This bit

always returns 0h when read, write operations have no effect.

PME Enable (PME_EN): This bit is 0 to indicate that PME# assertion

from D3 (cold) is disabled.

7:2

00h

Reserved

1:0

00b

Power State (PWRSTAT): This field indicates the current power state

of the IGD and can be used to set the IGD into a new power state. If

software attempts to write an unsupported state to this field, write

operation must complete normally on the bus, but the data is

discarded and no state change occurs. On a transition from D3 to D0

the graphics controller is optionally reset to initial values.

00 = D0 (Default)

01 = D1 (Not Supported)

10 = D2 (Not Supported)

11 = D3

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