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82G33 Datasheet(PDF) 282 Page - Intel Corporation |
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82G33 Datasheet(HTML) 282 Page - Intel Corporation |
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282 / 437 page  Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 282 Datasheet 8.2.22 HSRW—Mirror of Dev2 Func0 Hardware Scratch Read Write B/D/F/Type: 0/2/1/PCI Address Offset: 60–61h Default Value: 0000h Access: RO Size: 16 bits Bit Access & Default Description 15:0 RO 0000h Reserved 8.2.23 GDRST—Mirror of Dev2 Func0 Graphics Reset B/D/F/Type: 0/2/1/PCI Address Offset: C0h Default Value: 00h Access: RO Size: 8 bits This register is a mirror of the Graphics Reset Register in Device 2. Bit Access & Default Description 7:4 RO 0h Reserved 3:2 RO 00b Graphics Reset Domain (GRDOM): 00 = Full Graphics Reset will be performed (both render and display clock domain resets asserted 01 = Reserved (Invalid Programming) 10 = Reserved (Invalid Programming) 11 = Reserved (Invalid Programming) 1 RO 0b Reserved |
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