82G33 datasheet(283/437 Pages) INTEL

283 / 437 page

Integrated Graphics Device Registers (D2:F0,F1)

(Intel® 82Q35, 82Q33, 82G33 GMCH Only)

Datasheet

283

Bit

Access &

Default

Description

Graphics Reset (GDR): Setting this bit asserts graphics-only reset.

The clock domains to be reset are determined by GRDOM. Hardware

resets this bit when the reset is complete. Setting this bit without

waiting for it to clear, is undefined behavior.

Once this bit is set to a 1, all GFX core MMIO registers are returned to

power on default state. All Ring buffer pointers are reset, command

stream fetches are dropped and ongoing render pipeline processing is

halted, state machines and State Variables returned to power on

default state. If the Display is reset, all display engines are halted

(garbage on screen). VGA memory is not available; Store DWords and

interrupts are not ensured to be completed. Device #2 IO registers

are not available.

Device 2 Configuration registers continue to be available while

Graphics reset is asserted.

This bit is hardware auto-clear.

8.2.24

PMCAPID—Mirror of Fun 0 Power Management

Capabilities ID

B/D/F/Type:

0/2/1/PCI

Address Offset:

D0–D1h

Default Value:

0001h

Access:

Size:

16 bits

This register is a mirror of function 0 with the same R/W attributes. The hardware

implements a single physical register common to both functions 0 and 1.

Bit

Access &

Default

Description

15:8

00h

Next Capability Pointer (NEXT_PTR): This contains a pointer to

next item in capabilities list. This is the final capability in the list and

must be set to 00h.

7:0

01h

Capability Identifier (CAP_ID): SIG defines this ID is 01h for power

management.

82G33 Datasheet(PDF) 283 Page - Intel Corporation

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