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82G33 Datasheet(PDF) 286 Page - Intel Corporation |
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82G33 Datasheet(HTML) 286 Page - Intel Corporation |
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286 / 437 page ![]() Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33, 82G33 GMCH Only) 286 Datasheet 8.2.27 SWSMI—Mirror of Func0 Software SMI B/D/F/Type: 0/2/1/PCI Address Offset: E0–E1h Default Value: 0000h Access: RO Size: 16 bits As long as there is the potential that DVO port legacy drivers exist which expect this register at this address, D2:F0 address E0h–E1h must be reserved for this register. Bit Access & Default Description 15:8 RO 00h Software Scratch Bits (SWSB): 7:1 RO 00h Software Flag (SWF): This field is used to indicate caller and SMI function desired, as well as return result. 0 RO 0b GMCH Software SMI Event (GSSMIE): When Set, this bit will trigger an SMI. Software must write a 0 to clear this bit. § |
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