82G33 datasheet(290/437 Pages) INTEL

290 / 437 page

Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

290

Datasheet

9.1.2

CMD— Command

B/D/F/Type:

0/3/0/PCI

Address Offset:

04–05h

Default Value:

0000h

Access:

RO, RW

Size:

16 bits

Bit

Access &

Default

Description

15:11

00000b

Reserved

Interrupt Disable (ID): Disables this device from generating PCI line

based interrupts. This bit does not have any effect on MSI operation.

Fast Back-to-Back Enable (FBE): Not implemented, hardwired to 0.

SERR# Enable (SEE): Not implemented, hardwired to 0.

Wait Cycle Enable (WCC): Not implemented, hardwired to 0.

Parity Error Response Enable (PEE): Not implemented, hardwired

to 0.

VGA Palette Snooping Enable (VGA): Not implemented, hardwired

to 0

Memory Write and Invalidate Enable (MWIE): Not implemented,

hardwired to 0.

Special Cycle Enable (SCE): Not implemented, hardwired to 0.

Bus Master Enable (BME): This bit controls the HECI host

controller's ability to act as a system memory master for data

transfers. When this bit is cleared, HECI bus master activity stops and

any active DMA engines return to an idle condition.

1 = Enable

0 = Disable. HECI is blocked from generating MSI to the host

processor.

Note that this bit does not block HECI accesses to ME-UMA (i.e., writes

or reads to the host and ME circular buffers through the read window

and write window registers still cause ME backbone transactions to ME-

UMA).

Memory Space Enable (MSE): This bit controls access to the HECI

host controller’s memory mapped register space.

0 = Disable

1= Enable

I/O Space Enable (IOSE): Not implemented, hardwired to 0.

82G33 Datasheet(PDF) 290 Page - Intel Corporation

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