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82G33 Datasheet(PDF) 293 Page - Intel Corporation |
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82G33 Datasheet(HTML) 293 Page - Intel Corporation |
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293 / 437 page  Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Datasheet 293 9.1.7 MLT— Master Latency Timer B/D/F/Type: 0/3/0/PCI Address Offset: 0Dh Default Value: 00h Access: RO Size: 8 bits Bit Access & Default Description 7:0 RO 00h Master Latency Timer (MLT): Not implemented, hardwired to 0. 9.1.8 HTYPE— Header Type B/D/F/Type: 0/3/0/PCI Address Offset: 0Eh Default Value: 80h Access: RO Size: 8 bits Bit Access & Default Description 7 RO 1b Multi-Function Device (MFD): Indicates the HECI host controller is part of a multi-function device. 6:0 RO 0000000b Header Layout (HL): Indicates that the HECI host controller uses a target device layout. |
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