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82G33 Datasheet(PDF) 297 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 297 Page - Intel Corporation

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
Datasheet
297
9.1.17
PC— PCI Power Management Capabilities
B/D/F/Type:
0/3/0/PCI
Address Offset:
52–53h
Default Value:
C803h
Access:
RO
Size:
16 bits
Bit
Access &
Default
Description
15:11
RO
11001b
PME_Support (PSUP): Indicates the states that can generate PME#.
HECI can assert PME# from any D-state except D1 or D2 which are not
supported by HECI.
10
RO
0b
D2_Support (D2S): The D2 state is not supported for the HECI host
controller.
9
RO
0b
D1_Support (D1S): The D1 state is not supported for the HECI host
controller.
8:6
RO
000b
Aux_Current (AUXC): Reports the maximum Suspend well current
required when in the D3COLD state. Value of TBD is reported.
5
RO
0b
Device Specific Initialization (DSI): Indicates whether device-
specific initialization is required.
4
RO
0b
Reserved
3
RO
0b
PME Clock (PMEC): Indicates that PCI clock is not required to
generate PME#.
2:0
RO
011b
Version (VS): Indicates support for Revision 1.2 of the PCI Power
Management Specification.



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