82G33 datasheet(301/437 Pages) INTEL

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

Datasheet

301

9.1.23

MD— Message Signaled Interrupt Message Data

B/D/F/Type:

0/3/0/PCI

Address Offset:

98–99h

Default Value:

0000h

Access:

Size:

16 bits

Bit

Access &

Default

Description

15:0

0000h

Data (Data): This 16-bit field is programmed by system software if

MSI is enabled. Its content is driven onto the FSB during the data

phase of the MSI memory write transaction.

9.1.24

HIDM—HECI Interrupt Delivery Mode

B/D/F/Type:

0/3/0/PCI

Address Offset:

A0h

Default Value:

00h

Access:

Size:

8 bits

BIOS Optimal Default

00h

This register is used to select interrupt delivery mechanism for HECI to Host processor

interrupts.

Bit

Access &

Default

Description

7:2

Reserved

1:0

00b

HECI Interrupt Delivery Mode (HIDM): These bits control what type

of interrupt the HECI will send when ME FW writes to set the M_IG bit

in AUX space. They are interpreted as follows:

00 = Generate Legacy or MSI interrupt

01 = Generate SCI

10 = Generate SMI

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