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82G33 Datasheet(PDF) 303 Page - Intel Corporation |
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82G33 Datasheet(HTML) 303 Page - Intel Corporation |
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303 / 437 page ![]() Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Datasheet 303 9.2.1 ID— Identifiers B/D/F/Type: 0/3/1/PCI Address Offset: 00–03h Default Value: 29758086h Access: RO Size: 32 bits Bit Access & Default Description 31:16 RO 2975h Device ID (DID): Indicates what device number assigned by Intel. 15:0 RO 8086h Vendor ID (VID): 16-bit field which indicates Intel is the vendor, assigned by the PCI SIG. 9.2.2 CMD— Command B/D/F/Type: 0/3/1/PCI Address Offset: 04–05h Default Value: 0000h Access: RO, RW Size: 16 bits Bit Access & Default Description 15:11 RO 00000b Reserved 10 RW 0b Interrupt Disable (ID): Disables this device from generating PCI line based interrupts. This bit does not have any effect on MSI operation. 0 = Enable 1 = Disable 9 RO 0b Fast Back-to-Back Enable (FBE): Not implemented, hardwired to 0. 8 RO 0b SERR# Enable (SEE): Not implemented, hardwired to 0. 7 RO 0b Wait Cycle Enable (WCC): Not implemented, hardwired to 0. 6 RO 0b Parity Error Response Enable (PEE): Not implemented, hardwired to 0. 5 RO 0b VGA Palette Snooping Enable (VGA): Not implemented, hardwired to 0 4 RO 0b Memory Write and Invalidate Enable (MWIE): Not implemented, hardwired to 0. 3 RO 0b Special Cycle Enable (SCE): Not implemented, hardwired to 0. |
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