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82G33 Datasheet(PDF) 304 Page - Intel Corporation |
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82G33 Datasheet(HTML) 304 Page - Intel Corporation |
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304 / 437 page  Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) 304 Datasheet Bit Access & Default Description 2 RW 0b Bus Master Enable (BME): This bit controls the HECI host controller's ability to act as a system memory master for data transfers. When this bit is cleared, HECI bus master activity stops and any active DMA engines return to an idle condition. 0 = Disable. HECI is blocked from generating MSI to the host processor. 1 = Enable. Note that this bit does not block HECI accesses to ME-UMA (i.e., writes or reads to the host and ME circular buffers through the read window and write window registers still cause ME backbone transactions to ME- UMA). 1 RW 0b Memory Space Enable (MSE): This bit controls access to the HECI host controller’s memory mapped register space. 0 = Disable 1 = Enable 0 RO 0b I/O Space Enable (IOSE): Not implemented, hardwired to 0. |
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