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82G33 Datasheet(PDF) 295 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 295 Page - Intel Corporation

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
Datasheet
295
9.1.11
CAP— Capabilities Pointer
B/D/F/Type:
0/3/0/PCI
Address Offset:
34h
Default Value:
50h
Access:
RO
Size:
8 bits
Bit
Access &
Default
Description
7:0
RO
50h
Capability Pointer (CP): Indicates the first capability pointer offset. It
points to the PCI power management capability offset.
9.1.12
INTR— Interrupt Information
B/D/F/Type:
0/3/0/PCI
Address Offset:
3C–3Dh
Default Value:
0100h
Access:
RO, RW
Size:
16 bits
Bit
Access &
Default
Description
15:8
RO
01h
Interrupt Pin (IPIN): This indicates the interrupt pin the HECI host
controller uses. The value of 01h selects INTA# interrupt pin.
Note: As HECI is an internal device in the GMCH, the INTA# pin is
implemented as an INTA# message to the ICH9.
7:0
RW
00h
Interrupt Line (ILINE): Software written value to indicate which
interrupt line (vector) the interrupt is connected to. No hardware action
is taken on this register.
9.1.13
MGNT— Minimum Grant
B/D/F/Type:
0/3/0/PCI
Address Offset:
3Eh
Default Value:
00h
Access:
RO
Size:
8 bits
Bit
Access &
Default
Description
7:0
RO
00h
Grant (GNT): Not implemented, hardwired to 0.



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