82G33 datasheet(292/437 Pages) INTEL

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)

292

Datasheet

9.1.4

RID— Revision ID

B/D/F/Type:

0/3/0/PCI

Address Offset:

08h

Default Value:

00h

Access:

Size:

8 bits

Bit

Access &

Default

Description

7:0

00h

Revision ID (RID): Indicates stepping of the HECI host controller.

Refer to the Intel® 3 Series Express Chipset Family Specification Update

for the value of the Revision ID register.

9.1.5

CC— Class Code

B/D/F/Type:

0/3/0/PCI

Address Offset:

09–0Bh

Default Value:

078000h

Access:

Size:

24 bits

Bit

Access &

Default

Description

23:16

07h

Base Class Code (BCC): Indicates the base class code of the HECI

host controller device.

15:8

80h

Sub Class Code (SCC): Indicates the sub class code of the HECI host

controller device.

7:0

00h

Programming Interface (PI): Indicates the programming interface of

the HECI host controller device.

9.1.6

CLS— Cache Line Size

B/D/F/Type:

0/3/0/PCI

Address Offset:

0Ch

Default Value:

00h

Access:

Size:

8 bits

Bit

Access &

Default

Description

7:0

00h

Cache Line Size (CLS): Not implemented, hardwired to 0.

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