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82G33 Datasheet(PDF) 291 Page - Intel Corporation |
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82G33 Datasheet(HTML) 291 Page - Intel Corporation |
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291 / 437 page ![]() Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) Datasheet 291 9.1.3 STS— Device Status B/D/F/Type: 0/3/0/PCI Address Offset: 06–07h Default Value: 0010h Access: RO Size: 16 bits Bit Access & Default Description 15 RO 0b Detected Parity Error (DPE): Not implemented, hardwired to 0. 14 RO 0b Signaled System Error (SSE): Not implemented, hardwired to 0. 13 RO 0b Received Master-Abort (RMA): Not implemented, hardwired to 0. 12 RO 0b Received Target Abort (RTA): Not implemented, hardwired to 0. 11 RO 0b Signaled Target-Abort (STA): Not implemented, hardwired to 0. 10:9 RO 00b DEVSEL# Timing (DEVT): These bits are hardwired to 00. 8 RO 0b Master Data Parity Error Detected (DPD): Not implemented, hardwired to 0. 7 RO 0b Fast Back-to-Back Capable (FBC): Not implemented, hardwired to 0. 6 RO 0b Reserved 5 RO 0b 66 MHz Capable (C66): Not implemented, hardwired to 0. 4 RO 1b Capabilities List (CL): Indicates the presence of a capabilities list, hardwired to 1. 3 RO 0b Interrupt Status (IS): Indicates the interrupt status of the device 0 = Not asserted 1 = Asserted 2:0 RO 000b Reserved |
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